1. The Field of the Invention
This invention relates to design layout for metal lines of an integrated circuit, an ASIC/SRAM or DRAM structure, and more particularly relates to deposition of an intermetal dielectric oxide layer over metal lines so as to leave a fully planarized surface of the intermetal dielectric layer through standardization of spacing between metal features situated on a substrate.
2. The Relevant Technology
Conventionally designed metal line layouts of integrated circuits (IC) structures necessitate that, after metal etching, large spaces will be left between nearest parallel electrically isolated metal lines. These spacings are random in size and have a great variety of dimensions. When an intermetal dielectric layer, such as an oxide, is deposited over the metal lines having random spacing therebetween, the top surface of the intermetal dielectric (IDL) will have an altitude of the thickness of the metal features (T.sub.met) plus the thickness of the intermetal dielectric layer (T.sub.idl) In those areas where there are no metal features but only open space, the altitude of the top surface of the intermetal dielectric layer will be T.sub.idl.
FIG. 1 depicts a conventional integrated circuit structure having a metal line layout thereon. In FIG. 1, a substrate 10 has an intermetal dielectric layer 12 situated thereon. Intermetal dielectric layer 12 is also situated upon a series of metal lines 14. Metal lines 14 are placed upon substrate 10 by a process known as metal patterning. After contact formation, a thin layer of conducting metal is deposited by conventional techniques over the substrate. Unwanted portions of the metal film are removed by photomasking and etch procedure or by lift-off. A heat treatment step may be performed to flow material into contacts, or to alloy the remaining metal film, which are called metal lines, so as to ensure good electrical contact between the metal film and the underlying contact areas.
After the forgoing metal patterning process, or variations thereof, each metal line 14 has a thickness T.sub.met 16 and has a width.gtoreq.W.sub.met 18. The thickness of intermetal dielectric layer 12 is T.sub.idl 20. The altitude of the top surface of the intermetal dielectric layer 12 is seen as T.sub.met +T.sub.idl, seen at 22.
FIG. 1 shows intermetal dielectric layer 12 as being nonplanarized and having both large and small trenches in IDL 12. Where spacing between two metal features is small, a narrow or fused trench 24 results. Trench 24 has a narrow width and a high height thereto. If the trench is filled with IDL the final structure has a height of T.sub.met +T.sub.idl. Where the spacing between metal features is wide, a nonplanar structure with heights of T.sub.idl and T.sub.idl +T.sub.met results, as in 26. FIG. 1 also shows that the surface of IDL 12 is constant in large areas where no metal features exist, such as the right-hand side of FIG. 1 showing the top surface of IDL 12 to have an altitude of T.sub.idl, as seen at 20.
After a conventional metal line layout, altitude differences exist in the top surface of the intermetal dielectric layer deposited thereover. The processing that tries to minimize or eliminate the different altitudes of the top surface of the IDL in the different areas of the metal line design layout is called planarization. Conventional planarization requires a complicated series of process steps, which increases cost, and reduces yield in manufacturing.
When the altitude of the top surface of an IDL or metal film varies, it is more difficult to print small features using photolithography because the photolithography equipment has a limited depth of focus. Areas of different altitude of the top surface of the IDL will print differently in size and resolution of features during the photolithography. Metal stringers can remain after dry chemistry metal etching along the slopes of the nonplanar surface so as to cause an electrical short between adjacent metal lines. Additionally, transitions between areas of different altitude of the layer below a metal film 14 will result in poor step coverage at trenches 24 of the metal layer 14 in these areas, as seen in FIG. 2.
Conventional planarization often requires a relatively thick IDL layer 12 to guarantee an uninterrupted IDL film over a metal pattern 14 for electrical isolation. This thick IDL layer 12 can complicate the formation of the next vias due to high aspect ratios, as is seen at 13 in FIG. 3 for a second metal layer MET-2. Conversely, a low aspect ratio at 13, as seen in FIG. 4, is easier for metal layer MET-2 to fill.
A random distribution of metal pattern may lead to an unbalanced distribution of areas with metal features and without metal features which can cause nonuniformities in the etching process.
Accordingly, it would be an advance in the art to planarize the IDL with as few process steps as possible, so as to be beneficial in the photolithography metal deposition and etching process steps that follow the deposition of the IDL.